1. Field of the Invention
The present invention relates to a configuration and method having a first device and a second device connected to the first device through a cross bar, in which the first device can access the second device through the cross bar for reading and/or writing.
Such a configuration may, but need not, be entirely or partially a component of a programmable unit such as a microprocessor, microcontroller, signal processor, or the like.
The first device is a device that is referred to in the following text as a master unit and can initiate a transfer of data from or to the second device, that is to say, a read or write access to the second device; the first device may, therefore, be, by way of example, but need not necessarily be, a CPU or a DMA controller of a programmable unit.
The second device is a device that is referred to as a slave unit in the following text and emits data requested by the master unit to the master unit, or receives data supplied to it from the master unit and further processes or stores this data; the second device may, thus, by way of example, but need not necessarily be, a memory.
The master unit and the slave unit need not be connected directly to the cross bar. The connection can also be provided through a bus interface, a bus bridge, or some other interface.
Normally, not only a master unit and a slave unit, but a number of master units and/or a number of slave units, are connected to a cross bar, and can be connected to one another through the cross bar.
The fundamental construction of a configuration such as this is shown in FIG. 2.
The configuration shown in FIG. 2 includes a first master unit M11, a second master unit M12, a third master unit M13, a first slave unit S11, a second slave unit S12, a third slave unit S13, and a cross bar XB1.
The master units M11 to M13 and the slave units S11 to S13 are connected to one another through the cross bar XB1. To be more precise, the connection is done such that the master units M11 to M13 and the slave units S11 to S13 are connected by lines or buses, which are not shown in any more detail in FIG. 2, to associated connections of the cross bar XB1, and such that the connections of the cross bar XB1 to which the master units M11 to M13 are connected are each connected to all the connections to which the slave units S11 to S13 are connected.
In addition to the internal connections that have been mentioned, the cross bar XB1 contains arbiters A11 to A13 and multiplexers MUX11 to MUX13.
The arbiters A11 to A13 are connected upstream of the connections of the cross bar XB1 to which the slave units S11 to S13 are connected. To be more precise, this is done such that:                the arbiter A11 is connected upstream of that connection of the cross bar XB1 to which the slave unit S11 is connected;        the arbiter A12 is connected upstream of that connection of the cross bar XB1 to which the slave unit S12 is connected; and        the arbiter A13 is connected upstream of that connection of the cross bar XB1 to which the slave unit S13 is connected.        
The arbiters A11 to A13 monitor whether any of the master units M11 to M13 are requesting a connection for the slave unit that is connected to that connection of the cross bar that is connected upstream of the respective arbiter, and produce a connection between the relevant slave unit and the master unit that has requested the connection, when an appropriate connection request is present and the slave unit is not currently connected to any other master unit or—for whatever reason—must be connected to another master unit prior to this.
The multiplexers MUX11 to MUX13 are connected upstream of those connections of the cross bar XB1 to which the master units M11 to M13 are connected. To be more precise, the connection is done such that:                the multiplexer MUX11 is connected upstream of that connection of the cross bar XB1 to which the master unit M11 is connected;        the multiplexer MUX12 is connected upstream of that connection of the cross bar XB1 to which the master unit M12 is connected; and        the multiplexer MUX13 is connected upstream of that connection of the cross bar XB1 to which the master unit M13 is connected.        
The multiplexers MUX11 to MUX13 are controlled by the arbiters A11 to A13, to be precise, in such a manner that data that is emitted from the slave units is in each case supplied to the master unit, to be more precise, only that master unit that has requested the connection for the relevant slave unit.
For the sake of completeness, it should be mentioned that at least those lines by which the master units M11 to M13 request a connection for one of the slave units S11 to S13 are not routed through the multiplexers.
It is also possible for different master units to be connected to different slave units at the same time. For example, the first master unit M11 can be connected to the second slave unit S12, the second master unit M12 can be connected to the first slave unit S11, and the third master unit M13 can be connected to the third slave unit S13 at the same time through those internal connections of the cross bar XB1 that are shown by thicker lines.
The cross bar XB1, thus, allows data to be transmitted very efficiently between the devices connected to it.
However, this is true only when the execution of mutually corresponding actions, which one master unit can request from different slave units, take place from the point of view of the master unit in accordance with the same scheme, in particular, having the same timing.
For example, this is not the case when the master unit receives the data requested from a first slave unit after n clock cycles and receives the data requested from a second slave unit later, that is to say, only after n+m clock cycles. This may occur, for example, when the second slave unit requires a longer time to emit the data requested from it than the first slave unit. If differences such as these are present:                the special features of the respective slave units, in particular, the reaction times of the slave units, must be set in the master unit to the requirements emitted from the master unit, or        the cross bar must contain so-called wait state generators, which produce so-called wait states to signal to the master units that the slave unit has not yet reacted to the request from the master unit.        
However, this makes the design and operation of the master units and of the cross bar more complex and complicated.
Furthermore, the various reaction times of the slave units to a request from a master unit do not depend only on the design of the slave unit but also on the signal delay times between the master units and the slave units.
The length of the signal delay times depends, inter alia, on the length of the connecting lines between the master units and/or the slave units and the cross bar, thus, the signal delay times may differ considerably from one another. Furthermore, poor signal delay times may make it necessary to insert one or more pipeline stages, in the form of flip-flops for example, in the signal paths between certain master units and the cross bar and/or between certain slave units and the cross bar, and these pipeline stages may result in additional delays in the reaction of the slave units to a request from a master unit.
Additional delays may, furthermore, also occur as a result of the master units and the slave units not being connected directly to the cross bar, through bus interfaces, bus bridges, or the like.
If such additional delays are present, and these delays are also intended to be taken into account by appropriate settings of the master units or of the wait state generators for the cross bar, the design and operation of the master units and of the cross bar becomes even more complex and complicated.
Another solution to the problems caused by the additional delays is for the clock frequency at which the data is transmitted between the devices connected to the cross bar to be reduced sufficiently that the different signal delay times have no effect on the reaction times, and no pipeline stages are required either. However, in this case, the system operates more slowly than the speed at which it could actually operate.